Tech Lead/Software Architect – 5G massiveMIMO (L1)

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Tech Lead/Software Architect – 5G massiveMIMO (L1)

Bangalore
Posted on 01 Mar 2022

Location:

  • Bangalore

Role Summary and Responsibilities:

  • Translate L1 feature requirement set to L1 compoenet SW architectures and high level designs
  • In Architect role, create SW architecture specifications covering functional and performance requirements
  • From high level designs, develop low-level design specifications for target SDR/DSP platforms
  • Own, implement low level designs on the SDR/DSP based platforms following scalability and testability guidelines established in the organization
  • Create block level, sub-system and system level test suits and testability criterions and take active part in implementation verifications at every level till end to end.
  • Participat in troubleshooting in the lab and field; work on resolving field reported issues and radio integration, performance and conformance tests
  • Closely work with radio system designers for systems level asepcts and with HW/FPGA teams for HW-SW interface designs

Job Requirements:

  • Over 4-12 years of engineering experience and BE/BTech/ME/MTech from in EE/ECE/CSE(or equivalent) from recognized universities
  • Experience in 4G or 5G or massiveMIMO. Experience in Intel FlexRAN is a plus
  • Strong experience in specifications, design and implementation of real time signal processing designs in C/C++ on DSP and and x86 based processor and platforms
  • Experience in L1 and protocol software archtectures designs for 5G and 3GPP LTE cellular systems (ideally on the base station side)
  • Experience in real time debugging for enodeB/UE, log analysis like qxdm/qcat
  • Experience with lab instruments like Spectrum Analyzer, Signal Generator, fading emulators etc.
  • Experienced in handling Matlab design and translate them to embedded SWs on real time OS
  • Familiarity with build systems and source control SWs and tools
  • Experience in SW design for multi-threading processors
  • Understanding of processor subsystems, memory and bus architectures
  • Experience defining system architectures and exploring technical feasibility trade-offs